Designing analog circuits in CMOS

The evolution in CMOS technology dictated by Moore's Law is clearly beneficial for designers of digital circuits, but it presents difficult challenges, such as lowered nominal supply voltages, for their peers in the analog world who want to keep pace with this rapid progression. This article discusses a number of significant items for analog designs in modern and future CMOS processes and possible ways to maintain performance

Analog Circuits in Ultra-Deep-Submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

HLA: What's in a name? A commentary on HLA nomenclature development over the years

This paper discusses the influence of different sources of DC parametric mismatch in an LDMOS. By comparing measurements and statistical simulations the impact on mismatch of the most important fluctuation causes is qualitatively evaluated. We demonstrate that, whereas the shape of the doping profile in the channel has little effect, both interface states and series resistances play a major role in the mismatch. This work forms a crucial first step towards a better understanding of the random fluctuation mechanisms present in LDMOS devices used in MMICs

Mismatch sources in LDMOS devices

This paper discusses the influence of different sources of DC parametric mismatch in an LDMOS. By comparing measurements and statistical simulations the impact on mismatch of the most important fluctuation causes is qualitatively evaluated. We demonstrate that, whereas the shape of the doping profile in the channel has little effect, both interface states and series resistances play a major role in the mismatch. This work forms a crucial first step towards a better understanding of the random fluctuation mechanisms present in LDMOS devices used in MMICs

Analog Circuits in Ultra-Deep Sub-Micron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

Designing outside rail constraints

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors

Characterization and modeling of hot carrier-induced variability in subthreshold region

We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45- and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability

Impact of hot carriers on nMOSFET variability in 45- and 65-nm CMOS technologies

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced V(T) shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes